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INTEGRATED CIRCUITS
80C31/80C51/87C51 CMOS single-chip 8-bit microcontrollers
Product specification IC20 Data Handbook 1996 Aug 16
Philips Semiconductors
Philips Semiconductors
Product specification
CMOS single-chip 8-bit microcontrollers
80C31/80C51/87C51
DESCRIPTION
The Philips 80C31/80C51/87C51 is a high-performance microcontroller fabricated with Philips high-density CMOS technology. The CMOS 8XC51 is functionally compatible with the NMOS 8031/8051 microcontrollers. The Philips CMOS technology combines the high speed and density characteristics of HMOS with the low power attributes of CMOS. Philips epitaxial substrate minimizes latch-up sensitivity. The 8XC51 contains a 4k x 8 ROM (80C51) EPROM (87C51), a 128 x 8 RAM, 32 I/O lines, two 16-bit counter/timers, a five-source, two-priority level nested interrupt structure, a serial I/O port for either multi-processor communications, I/O expansion or full duplex UART, and on-chip oscillator and clock circuits. In addition, the device has two software selectable modes of power reduction--idle mode and power-down mode. The idle mode freezes the CPU while allowing the RAM, timers, serial port, and interrupt system to continue functioning. The power-down mode saves the RAM contents but freezes the oscillator, causing all other chip functions to be inoperative.
PIN CONFIGURATIONS
P1.0 1 P1.1 2 P1.2 3 P1.3 4 P1.4 5 P1.5 6 P1.6 7 P1.7 8 RST 9 RxD/P3.0 10 TxD/P3.1 11 INT0/P3.2 12 INT1/P3.3 13 T0/P3.4 14 CERAMIC AND PLASTIC DUAL IN-LINE PACKAGE 40 V CC 39 P0.0/AD0 38 P0.1/AD1 37 P0.2/AD2 36 P0.3/AD3 35 P0.4/AD4 34 P0.5/AD5 33 P0.6/AD6 32 P0.7/AD7 31 EA/VPP 30 ALE/PROG 29 PSEN 28 P2.7/A15 27 P2.6/A14 26 P2.5/A13 25 P2.4/A12 24 P2.3/A11 23 P2.2/A10 22 P2.1/A9 21 P2.0/A8
FEATURES
T1/P3.5 15 WR/P3.6 16 RD/P3.7 17 XTAL2 18 XTAL1 19 VSS 20
* 8031/8051 compatible
- 4k x 8 ROM (80C51) - 4k x 8 EPROM (87C51) - ROMless (80C31) - 128 x 8 RAM - Two 16-bit counter/timers - Full duplex serial channel - Boolean processor
6
1
40
* Memory addressing capability
- 64k ROM and 64k RAM
7 CERAMIC AND PLASTIC LEAD CHIP CARRIER
39
* Power control modes:
- Idle mode - Power-down mode
17
29
* CMOS and TTL compatible * Five speed ranges at VCC = 5V
- 12MHz - 16MHz - 24MHz - 33MHz
1
18
28
44
34
33 PLASTIC QUAD FLAT PACK
* Five package styles * Extended temperature ranges * OTP package available
11
23
12
22
SU00001
SEE PAGE 3 FOR QFP AND LCC PIN FUNCTIONS.
1996 Aug 16
2
853-0169 17187
Philips Semiconductors
Product specification
CMOS single-chip 8-bit microcontrollers
80C31/80C51/87C51
CERAMIC AND PLASTIC LEADED CHIP CARRIER PIN FUNCTIONS
6 1 40
PLASTIC QUAD FLAT PACK PIN FUNCTIONS
44 34
7
39 1 LCC 33
PQFP
17
29
11
23
18
28
12 Pin 31 32 33 34 35 36 37 38 39 40 41 42 43 44 Function P2.7/A15 PSEN ALE/PROG NC* EA/VPP P0.7/AD7 P0.6/AD6 P0.5/AD5 P0.4/AD4 P0.3/AD3 P0.2/AD2 P0.1/AD1 P0.0/AD0 VCC Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Function P1.5 P1.6 P1.7 RST P3.0/RxD NC* P3.1/TxD P3.2/INT0 P3.3/INT1 P3.4/T0 P3.5/T1 P3.6/WR P3.7/RD XTAL2 XTAL1 Pin 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 Function VSS NC* P2.0/A8 P2.1/A9 P2.2/A10 P2.3/A11 P2.4/A12 P2.5/A13 P2.6/A14 P2.7/A15 PSEN
22 Pin 31 32 33 34 35 36 37 38 39 40 41 42 43 44 Function P0.6/AD6 P0.5/AD5 P0.4/AD4 P0.3/AD3 P0.2/AD2 P0.1/AD1 P0.0/AD0 VCC NC* P1.0 P1.1 P1.2 P.13 P1.4
Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Function NC* P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 RST P3.0/RxD NC* P3.1/TxD P3.2/INT0 P3.3/INT1
Pin 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
Function P3.4/T0 P3.5/T1 P3.6/WR P3.7/RD XTAL2 XTAL1 VSS NC* P2.0/A8 P2.1/A9 P2.2/A10 P2.3/A11 P2.4/A12 P2.5/A13 P2.6/A14
ALE/PROG NC* EA/VPP P0.7/AD7
* DO NOT CONNECT
SU00002
* DO NOT CONNECT
SU00003
LOGIC SYMBOL
VCC XTAL1 PORT 0 ADDRESS AND DATA BUS VSS
XTAL2
SECONDARY FUNCTIONS
RST EA/VPP PSEN ALE/PROG RxD TxD INT0 INT1 T0 T1 WR RD
PORT 3
PORT 2
PORT 1
ADDRESS BUS
SU00004
1996 Aug 16
3
Philips Semiconductors
Product specification
CMOS single-chip 8-bit microcontrollers
80C31/80C51/87C51
ORDERING INFORMATION
PHILIPS NORTH AMERICA EPROM SC87C51CCF40 SC87C51CCK44 SC87C51CCN40 SC87C51CCA44 SC87C51CCB44 SC87C51ACF40 SC87C51ACN40 SC87C51ACA44 SC87C51ACB44 SC87C51CGF40 SC87C51CGK44 SC87C51CGN40 SC87C51CGA44 SC87C51CGB44 SC87C51AGF40 SC87C51AGN40 SC87C51AGA44 SC87C51AGB44
DRAWING NUMBER DRAWING NUMBER
ROMless
ROM
TEMPERATURE RANGE oC AND PACKAGE1 0 to +70, Ceramic Dual In-line Package, UV 0 to +70, Ceramic Leaded Chip Carrier, UV
Freq MHz 3.5 to 12 3.5 to 12 3.5 to 12 3.5 to 12 3.5 to 12 3.5 to 12 3.5 to 12 3.5 to 12 3.5 to 12 3.5 to 16 3.5 to 16 3.5 to 16 3.5 to 16 3.5 to 16 3.5 to 16 3.5 to 16 3.5 to 16 3.5 to 16
0590B 1472A
SOT129-1 SOT187-2 SOT307-2
SC80C31BCCN40 SC80C31BCCA44 SC80C31BCCB44
SC80C51BCCN40 SC80C51BCCA44 SC80C51BCCB44
SOT129-1 SOT187-2 SOT307-2
0 to +70, Plastic Dual In-line Package, OTP 0 to +70, Plastic Leaded Chip Carrier, OTP 0 to +70, Plastic Quad Flat Pack, OTP -40 to +85, Ceramic Dual In-line Package, UV
0590B
SOT129-1 SOT187-2 SOT307-2
SC80C31BACN40 SC80C31BACA44 SC80C31BACB44
SC80C51BACN40 SC80C51BACA44 SC80C51BACB44
SOT129-1 SOT187-2 SOT307-2
-40 to +85, Plastic Dual In-line Package, OTP -40 to +85, Plastic Leaded Chip Carrier, OTP -40 to +85, Plastic Quad Flat Pack, OTP 0 to +70, Ceramic Dual In-line Package, UV 0 to +70, Ceramic Leaded Chip Carrier, UV
0590B 1472A
SOT129-1 SOT187-2 SOT307-2
SC80C31BCGN40 SC80C31BCGA44 SC80C31BCGB44
SC80C51BCGN40 SC80C51BCGA44 SC80C51BCGB44
SOT129-1 SOT187-2 SOT307-2
0 to +70, Plastic Dual In-line Package, OTP 0 to +70, Plastic Leaded Chip Carrier, OTP 0 to +70, Plastic Quad Flat Pack, OTP -40 to +85, Ceramic Dual In-line Package, UV
0590B
SOT129-1 SOT187-2 SOT307-2
SC80C31BAGN40 SC80C31BAGA44 SC80C31BAGB44
SC80C51BAGN40 SC80C51BAGA44 SC80C51BAGB44
SOT129-1 SOT187-2 SOT307-2
-40 to +85, Plastic Dual In-line Package, OTP -40 to +85, Plastic Leaded Chip Carrier, OTP -40 to +85, Plastic Quad Flat Pack, OTP
SC87C51CPF40 SC87C51CPK44 SC87C51CPN40 SC87C51CPA44
0590B 1472A
SOT129-1 SOT187-2
0 to +70, Ceramic Dual In-line Package, UV 0 to +70, Ceramic Leaded Chip Carrier, UV SC80C31BCPN40 SC80C31BCPA44 SC80C51BCPN40 SC80C51BCPA44
SOT129-1 SOT187-2
3.5 to 24 3.5 to 24 3.5 to 24 3.5 to 24
0 to +70, Plastic Dual In-line Package, OTP 0 to +70, Plastic Leaded Chip Carrier, OTP
SC87C51APF40 SC87C51APN40 SC87C51APA44
0590B
SOT129-1 SOT187-2
-40 to +85, Ceramic Dual In-line Package, UV SC80C31BAPN40 SC80C31BAPA44 SC80C51BAPN40 SC80C51BAPA44
SOT129-1 SOT187-2
-40 to +85, Plastic Dual In-line Package, OTP -40 to +85, Plastic Leaded Chip Carrier, OTP
3.5 to 24 3.5 to 24
SC87C51CYF40 SC87C51CYK44 SC87C51CYN40 SC87C51CYA44
0590B 1472A
SOT129-1 SOT187-2
0 to +70, Ceramic Dual In-line Package, UV 0 to +70, Ceramic Leaded Chip Carrier, UV SC80C31BCYN40 SC80C31BCYA44 SC80C51BCYN40 SC80C51BCYA44
SOT129-1 SOT187-2
3.5 to 33 3.5 to 33 3.5 to 33 3.5 to 33
0 to +70, Plastic Dual In-line Package, OTP 0 to +70, Plastic Leaded Chip Carrier, OTP
1. OTP = One Time Programmable EPROM. UV = UV Erasable EPROM 2. SOT311 replaced by SOT307-2.
1996 Aug 16
4
Philips Semiconductors
Product specification
CMOS single-chip 8-bit microcontrollers
80C31/80C51/87C51
ORDERING INFORMATION (Continued)
PHILIPS ROMless
(ORDER NUMBER)
ROMless
(MARKING NUMBER)
ROM
DRAWING NUMBER
TEMPERATURE RANGE oC AND PACKAGE1
Freq MHz
PCB80C31-2 N PCB80C31-2 A
PCB80C31BH2-12P
PCB80C51BH-2P
SOT129-1 SOT187-2 SOT307-22
0 to +70, Plastic Dual In-line Package, OTP 0 to +70, Plastic Leaded Chip Carrier, OTP 0 to +70, Plastic Quad Flat Pack, OTP
0.5 to 12 0.5 to 12 0.5 to 12
PCB80C31BH2-12WP PCB80C51BH-2WP PCB80C31BH2-12H PCB80C51BH-2H
PCB80C31-3 N PCB80C31-3 A
PCB80C31BH3-16P
PCB80C51BH-3P
SOT129-1 SOT187-2 SOT307-22
0 to +70, Plastic Dual In-line Package, OTP 0 to +70, Plastic Leaded Chip Carrier, OTP 0 to +70, Plastic Quad Flat Pack, OTP
1.2 to 16 1.2 to 16 1.2 to 16
PCB80C31BH3-16WP PCB80C51BH-3WP PCB80C31BH3-16H PCB80C51BH-3H
PCF80C31-3 N PCF80C31-3 A
PCF80C31BH3-16P PCF80C31BH3-16WP PCF80C31BH3-16H PCA80C31BH3-16P
PCF80C51BH-3P PCF80C51BH-3WP PCF80C51BH-3H PCA80C51BH-3P
SOT129-1 SOT187-2 SOT307-22 SOT129-1 SOT187-2
-40 to +85, Plastic Dual In-line Package, OTP -40 to +85, Plastic Leaded Chip Carrier, OTP -40 to +85, Plastic Quad Flat Pack, OTP -40 to +125, Plastic Dual In-line Package -40 to +125, Plastic Leaded Chip Carrier
1.2 to 16 1.2 to 16 1.2 to 16 1.2 to 16 1.2 to 16
PCA80C31BH3-16WP PCA80C51BH-3WP
PCB80C31-4 N PCB80C31-4 A
PCB80C31BH4-24P
PCB80C51BH-4P
SOT129-1 SOT187-2 SOT307-22
0 to +70, Plastic Dual In-line Package, OTP 0 to +70, Plastic Leaded Chip Carrier, OTP 0 to +70, Plastic Quad Flat Pack, OTP
1.2 to 24 1.2 to 24 1.2 to 24
PCB80C31BH4-24WP PCB80C51BH-4WP PCB80C31BH4-24H PCB80C51BH-4H
PCF80C31-4 N PCF80C31-4 A
PCF80C31BH4-24P PCF80C31BH4-24WP PCF80C31BH4-24H
PCF80C51BH-4P PCF80C51BH-4WP PCF80C51BH-4H
SOT129-1 SOT187-2 SOT307-22
-40 to +85, Plastic Dual In-line Package, OTP -40 to +85, Plastic Leaded Chip Carrier, OTP -40 to +85, Plastic Leaded Chip Carrier, OTP
1.2 to 24 1.2 to 24 1.2 to 24
PCB80C31-5 N PCB80C31-5 A PCB80C31-5 B
PCB80C31BH5-30P
PCB80C51BH-5P
SOT129-1 SOT187-2 SOT307-22
0 to +70, Plastic Dual In-line Package 0 to +70, Plastic Leaded Chip Carrier 0 to +70, Plastic Quad Flat Pack
1.2 to 33 1.2 to 33 1.2 to 33
PCB80C31BH5-30WP PCB80C51BH-5WP PCB80C31BH5-30H PCB80C51BH-5H
1996 Aug 16
5
Philips Semiconductors
Product specification
CMOS single-chip 8-bit microcontrollers
80C31/80C51/87C51
BLOCK DIAGRAM
P0.0-P0.7 P2.0-P2.7
PORT 0 DRIVERS VCC VSS RAM ADDR REGISTER RAM PORT 0 LATCH
PORT 2 DRIVERS
PORT 2 LATCH
ROM/EPROM
B REGISTER
ACC
STACK POINTER
TMP2
TMP1
PROGRAM ADDRESS REGISTER
ALU
PCON TL1
SCON TH0 SBUF
TMOD TL0 IE
TCON TH1 IP
BUFFER
PSW
INTERRUPT, SERIAL PORT AND TIMER BLOCKS
PC INCREMENTER
PROGRAM COUNTER PSEN ALE/PROG EA/VPP RST PD TIMING AND CONTROL INSTRUCTION REGISTER
DPTR
PORT 1 LATCH
PORT 3 LATCH
OSCILLATOR PORT 1 DRIVERS XTAL1 XTAL2 P1.0-P1.7 PORT 3 DRIVERS
P3.0-P3.7
SU00005
1996 Aug 16
6
Philips Semiconductors
Product specification
CMOS single-chip 8-bit microcontrollers
80C31/80C51/87C51
PIN DESCRIPTION
PIN NO. MNEMONIC VSS VCC P0.0-0.7 DIP 20 40 39-32 LCC 22 44 43-36 QFP 16 38 37-30 TYPE I I I/O Ground: 0V reference. Power Supply: This is the power supply voltage for normal, idle, and power-down operation. Port 0: Port 0 is an open-drain, bidirectional I/O port. Port 0 pins that have 1s written to them float and can be used as high-impedance inputs. Port 0 is also the multiplexed low-order address and data bus during accesses to external program and data memory. In this application, it uses strong internal pull-ups when emitting 1s. Port 0 also outputs the code bytes during program verification in the 87C51. External pull-ups are required during program verification. Port 1: Port 1 is an 8-bit bidirectional I/O port with internal pull-ups. Port 1 pins that have 1s written to them are pulled high by the internal pull-ups and can be used as inputs. As inputs, port 1 pins that are externally pulled low will source current because of the internal pull-ups. (See DC Electrical Characteristics: IIL). Port 1 also receives the low-order address byte during program memory verification. Port 2: Port 2 is an 8-bit bidirectional I/O port with internal pull-ups. Port 2 pins that have 1s written to them are pulled high by the internal pull-ups and can be used as inputs. As inputs, port 2 pins that are externally being pulled low will source current because of the internal pull-ups. (See DC Electrical Characteristics: IIL). Port 2 emits the high-order address byte during fetches from external program memory and during accesses to external data memory that use 16-bit addresses (MOVX @DPTR). In this application, it uses strong internal pull-ups when emitting 1s. During accesses to external data memory that use 8-bit addresses (MOV @Ri), port 2 emits the contents of the P2 special function register. Port 3: Port 3 is an 8-bit bidirectional I/O port with internal pull-ups. Port 3 pins that have 1s written to them are pulled high by the internal pull-ups and can be used as inputs. As inputs, port 3 pins that are externally being pulled low will source current because of the pull-ups. (See DC Electrical Characteristics: IIL). Port 3 also serves the special features of the 80C51 family, as listed below: RxD (P3.0): Serial input port TxD (P3.1): Serial output port INT0 (P3.2): External interrupt INT1 (P3.3): External interrupt T0 (P3.4): Timer 0 external input T1 (P3.5): Timer 1 external input WR (P3.6): External data memory write strobe RD (P3.7): External data memory read strobe Reset: A high on this pin for two machine cycles while the oscillator is running, resets the device. An internal diffused resistor to VSS permits a power-on reset using only an external capacitor to VCC. Address Latch Enable/Program Pulse: Output pulse for latching the low byte of the address during an access to external memory. In normal operation, ALE is emitted at a constant rate of 1/6 the oscillator frequency, and can be used for external timing or clocking. Note that one ALE pulse is skipped during each access to external data memory. This pin is also the program pulse input (PROG) during EPROM programming. Program Store Enable: The read strobe to external program memory. When the device is executing code from the external program memory, PSEN is activated twice each machine cycle, except that two PSEN activations are skipped during each access to external data memory. PSEN is not activated during fetches from internal program memory. External Access Enable/Programming Supply Voltage: EA must be externally held low to enable the device to fetch code from external program memory locations 0000H to 0FFFH. If EA is held high, the device executes from internal program memory unless the program counter contains an address greater than 0FFFH. This pin also receives the 12.75V programming supply voltage (VPP) during EPROM programming. Crystal 1: Input to the inverting oscillator amplifier and input to the internal clock generator circuits. Crystal 2: Output from the inverting oscillator amplifier. NAME AND FUNCTION
P1.0-P1.7
1-8
2-9
40-44, 1-3
I/O
P2.0-P2.7
21-28
24-31
18-25
I/O
P3.0-P3.7
10-17
11, 13-19
5, 7-13
I/O
10 11 12 13 14 15 16 17 RST 9
11 13 14 15 16 17 18 19 10
5 7 8 9 10 11 12 13 4
I O I I I I O O I
ALE/PROG
30
33
27
I/O
PSEN
29
32
26
O
EA/VPP
31
35
29
I
XTAL1 XTAL2
19 18
21 20
15 14
I O
1996 Aug 16
7
Philips Semiconductors
Product specification
CMOS single-chip 8-bit microcontrollers
80C31/80C51/87C51
Table 1.
SYMBOL ACC* AUXR# AUXR1# B* DPTR: DPH DPL IE* IP* IPH# P0* P1* P2* P3* PCON#1 PSW* SADDR# SADEN# SBUF SCON* SP TCON* T2MOD# TH0 TH1 TL0 TL1
80C52/80C54/80C58 Special Function Registers
DESCRIPTION Accumulator Auxiliary Auxiliary 1 (Note 2) B register Data Pointer (2 bytes) Data Pointer High Data Pointer Low Interrupt Enable Interrupt Priority Interrupt Priority High Port 0 Port 1 Port 2 Port 3 Power Control Program Status Word Slave Address Slave Address Mask Serial Data Buffer Serial Control Stack Pointer Timer Control Timer 2 Mode Control Timer High 0 Timer High 1 Timer Low 0 Timer Low 1 DIRECT ADDRESS E0H 8EH A2H F0H 83H 82H AF A8H B8H B7H 80H 90H A0H B0H 87H D0H A9H B9H 99H 9F 98H 81H 8F 88H C9H 8CH 8DH 8AH 8BH TF1 CF - 8E TR1 CE - 8D TF0 CD - 8C TR0 CC - 8B IE1 CB - 8A IT1 CA - 89 IE0 C9 T2OE 88 IT0 C8 DCEN xxxxxx00B 00H 00H 00H 00H 00H 00H
SM0/FE
BIT ADDRESS, SYMBOL, OR ALTERNATIVE PORT FUNCTION MSB LSB E7 - - F7 E6 - - F6 E5 - - F5 E4 - - F4 E3 - WUPD F3 E2 - 0 F2 E1 - - F1 E0 AO DPS F0
RESET VALUE 00H xxxxxxx0B xxxx00x0B 00H 00H 00H
AE EC BE - B6 - 86 AD6 96 - A6 AD14 B6 WR SMOD0 D6 AC
AD ET2 BD PT2 B5 PT2H 85 AD5 95 - A5 AD13 B5 T1 - D5 F0
AC ES BC PS B4 PSH 84 AD4 94 - A4 AD12 B4 T0 - D4 RS1
AB ET1 BB PT1 B3 PT1H 83 AD3 93 - A3 AD11 B3 INT1 GF1 D3 RS0
AA EX1 BA PX1 B2 PX1H 82 AD2 92 - A2 AD10 B2 INT0 GF0 D2 OV
A9 ET0 B9 PT0 B1 PT0H 81 AD1 91 T2EX A1 AD9 B1 TxD PD D1 -
A8 EX0 B8 PX0 B0 PX0H 80 AD0 90 T2 A0 AD8 B0 RxD IDL D0 P 00H 00H 00H xxxxxxxxB FFH 00xx0000B FFH FFH FFH x0000000B x0000000B 00H
EA BF - B7 - 87 AD7 97 - A7 AD15 B7 RD SMOD1 D7 CY
9E SM1
9D SM2
9C REN
9B TB8
9A RB8
99 TI
98 RI 00H 07H
TMOD Timer Mode 89H GATE * SFRs are bit addressable. # SFRs are modified from or added to the 80C51 SFRs. - Reserved bits. 1. Reset value depends on reset source. 2. Available only on SC80C51.
C/T
M1
M0
GATE
C/T
M1
M0
1996 Aug 16
8
Philips Semiconductors
Product specification
CMOS single-chip 8-bit microcontrollers
80C31/80C51/87C51
OSCILLATOR CHARACTERISTICS
XTAL1 and XTAL2 are the input and output, respectively, of an inverting amplifier. The pins can be configured for use as an on-chip oscillator, as shown in the logic symbol. To drive the device from an external clock source, XTAL1 should be driven while XTAL2 is left unconnected. There are no requirements on the duty cycle of the external clock signal, because the input to the internal clock circuitry is through a divide-by-two flip-flop. However, minimum and maximum high and low times specified in the data sheet must be observed.
IDLE MODE
In idle mode, the CPU puts itself to sleep while all of the on-chip peripherals stay active. The instruction to invoke the idle mode is the last instruction executed in the normal operating mode before the idle mode is activated. The CPU contents, the on-chip RAM, and all of the special function registers remain intact during this mode. The idle mode can be terminated either by any enabled interrupt (at which time the process is picked up at the interrupt service routine and continued), or by a hardware reset which starts the processor in the same manner as a power-on reset.
RESET
A reset is accomplished by holding the RST pin high for at least two machine cycles (24 oscillator periods), while the oscillator is running. To insure a good power-up reset, the RST pin must be high long enough to allow the oscillator time to start up (normally a few milliseconds) plus two machine cycles.
POWER-DOWN MODE
In the power-down mode, the oscillator is stopped and the instruction to invoke power-down is the last instruction executed. Only the contents of the on-chip RAM are preserved. A hardware reset is the only way to terminate the power-down mode. the control bits for the reduced power modes are in the special function register PCON. Table 2 shows the state of I/O ports during low current operating modes.
Table 2. External Pin Status During Idle and Power-Down Modes
MODE Idle Idle Power-down Power-down PROGRAM MEMORY Internal External Internal External ALE 1 1 0 0 PSEN 1 1 0 0 PORT 0 Data Float Data Float PORT 1 Data Data Data Data PORT 2 Data Address Data Data PORT 3 Data Data Data Data
ROM CODE SUBMISSION
When submitting ROM code for the 80C51, the following must be specified: 1. 4k byte user ROM data 2. 64 byte ROM encryption key (SC80C51 only) 3. ROM security bits (SC80C51 only). ADDRESS 0000H to 0FFFH 1000H to 101FH 1020H 1020H CONTENT DATA KEY SEC SEC BIT(S) 7:0 7:0 0 1 COMMENT User ROM Data ROM Encryption Key ROM Security Bit 1 ROM Security Bit 2
Security Bit 1: When programmed, this bit has two effects on masked ROM parts: 1. External MOVC is disabled, and 2. EA# is latched on Reset. Security Bit 2: When programmed, this bit inhibits Verify User ROM.
1996 Aug 16
9
Philips Semiconductors
Product specification
CMOS single-chip 8-bit microcontrollers
80C31/80C51/87C51
Electrical Deviations from Commercial Specifications for Extended Temperature Range (87C51) DC and AC parameters not included here are the same as in the commercial temperature range table.
DC ELECTRICAL CHARACTERISTICS
Tamb = -40C to +85C, VCC = 5V 10%, VSS = 0V (Philips North America SC87C51); For SC87C51 (33MHz only), Tamb = 0C to +70C, VCC = 5V 5% Tamb = -40C to +85C, VCC = 5V 10%, VSS = 0V (PCB80C31/51 and PCF80C31/51 Philips Parts Only) TEST SYMBOL VIL VIL VIL1 VIH VIH1 IIL ITL ICC PARAMETER Input low voltage, except EA (Philips North America) Input low voltage, except EA (Philips) Input low voltage to EA Input high voltage, except XTAL1, RST Input high voltage to XTAL1, RST Logical 0 input current, ports 1, 2, 3 Logical 1-to-0 transition current, ports 1, 2, 3 Power supply current: Active mode1 @ 16MHz (Philips PCB80C31/51, PCF80C31/51) Active mode @ 12MHz (Philips North America SC87C51) Idle mode2 @ 16MHz (Philips PCB80C31/51, PCF80C31/51) Idle mode @ 12MHz (Philips North America SC87C51) Power-down mode3 (Philips PCB80C31/51, PCF80C31/51) Power-down mode (Philips North America SC87C51) VIN = 0.45V VIN = 2.0V VCC = 4.5-5.5V 25 20 6.5 5 75 50 mA mA mA mA A A CONDITIONS MIN -0.5 -0.5 -0.5 0.2VCC+1 0.7VCC+0.1 LIMITS MAX 0.2VCC-0.15 0.2VCC-0.25 0.2VCC-0.45 VCC+0.5 VCC+0.5 -75 -750 UNIT V V V V V A A
NOTES: 1. The operating supply current is measured with all output pins disconnected; XTAL1 driven with tr = tf = 10ns; VIL = VSS + 0.5V; VIH = VCC - 0.5V; XTAL2 not connected; EA = RST = Port 0 = VCC. 2. The idle mode supply current is measured with all output pins disconnected; XTAL1 driven with tr = tf = 10ns; VIL = VSS + 0.5V; VIH = VCC - 0.5V; XTAL2 not connected; EA = Port 0 = VCC; RST = VSS. 3. The power-down current is measured with all output pins disconnected, XTAL2 not connected, EA = Port 0 = VCC; RST = VSS.
ABSOLUTE MAXIMUM RATINGS1, 2, 3
PARAMETER Operating temperature under bias Storage temperature range Voltage on EA/VPP pin to VSS Voltage on any other pin to VSS Maximum IOL per I/O pin Power dissipation (based on package heat transfer limitations, not device power consumption) RATING 0 to +70 or -40 to +85 -65 to +150 0 to +13.0 -0.5 to +6.5 15 1.5 UNIT C C V V mA W
NOTES: 1. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any conditions other than those described in the AC and DC Electrical Characteristics section of this specification is not implied. 2. This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive static charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated maxima. 3. Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to VSS unless otherwise noted.
1996 Aug 16
10
Philips Semiconductors
Product specification
CMOS single-chip 8-bit microcontrollers
80C31/80C51/87C51
Tamb = 0C to +70C or -40C to +85C, VCC = 5V 20%, VSS = 0V (PCB80C31/51 and PCF80C31/51) (12, 16, and 24MHz versions) Tamb = 0C to +70C or -40C to +85C, VCC = 5V 10%, VSS = 0V (87C51 12, 16, and 24MHz versions) (PCB80C31/51 33MHz version); For SC87C51 (33MHz only) Tamb = 0C to +70C, VCC = 5V 5% TEST SYMBOL VIL VIL1 VIH VIH1 VOL VOL1 VOH PARAMETER Input low voltage, except Input low voltage to EA7 EA7 CONDITIONS MIN -0.5 0 0.2VCC+0.9 0.7VCC IOL = PSEN3 1.6mA2 IOL = 3.2mA2 IOH = -60A, IOH = -25A IOH = -10A IOH = -800A, IOH = -300A IOH = -80A VIN = 0.45V See note 4 VIN = VIL or VIH See note 6 11.5 1.3 3 18 19 4.4 4 50 mA mA mA mA A 2.4 0.75VCC 0.9VCC 2.4 0.75VCC 0.9VCC -50 -650 10 LIMITS TYPICAL1 MAX 0.2VCC-0.1 0.2VCC-0.3 VCC+0.5 VCC+0.5 0.45 0.45 UNIT V V V V V V V V V V V V A A A
DC ELECTRICAL CHARACTERISTICS
Input high voltage, except XTAL1, RST7 Input high voltage, XTAL1, RST7 311
Output low voltage, ports 1, 2,
Output low voltage, port 0, ALE, PSEN11 Output high voltage, ports 1, 2, 3, ALE,
VOH1
Output high voltage (port 0 in external bus mode)
IIL ITL ILI ICC
Logical 0 input current, ports 1, 2, 37 Logical 1-to-0 transition current, ports 1, 2, 37 Input leakage current, port 0 Power supply Active mode @ 12MHz8 (Philips) Active mode @ 12MHz5 (Philips North America) Idle mode @ 12MHz9 (Philips) Idle mode @ 12MHz (Philips North America) Power-down mode10 (Philips and Philips North America) Internal reset pull-down resistor (Philips North America) (Philips) current:7
RRST
50 50
300 150
k k
CIO Pin capacitance12 10 pF NOTES: 1. Typical ratings are not guaranteed. The values listed are at room temperature, 5V. 2. Capacitive loading on ports 0 and 2 may cause spurious noise to be superimposed on the VOLs of ALE and ports 1 and 3. The noise is due to external bus capacitance discharging into the port 0 and port 2 pins when these pins make 1-to-0 transitions during bus operations. In the worst cases (capacitive loading > 100pF), the noise pulse on the ALE pin may exceed 0.8V. In such cases, it may be desirable to qualify ALE with a Schmitt Trigger, or use an address latch with a Schmitt Trigger STROBE input. IOL can exceed these conditions provided that no single output sinks more than 5mA and no more than two outputs exceed the test conditions. 3. Capacitive loading on ports 0 and 2 may cause the VOH on ALE and PSEN to momentarily fall below the 0.9VCC specification when the address bits are stabilizing. 4. Pins of ports 1, 2 and 3 source a transition current when they are being externally driven from 1 to 0. The transition current reaches its maximum value when VIN is approximately 2V. 5. ICCMAX at other frequencies (for Philips North America parts) is given by: Active mode: ICCMAX = 1.43 X FREQ + 1.90; Idle mode: ICCMAX = 0.14 X FREQ +2.31, where FREQ is the external oscillator frequency in MHz. ICCMAX is given in mA. See Figure 8. 6. See Figures 9 through 12 for ICC test conditions. 7. For Philips North America parts when Tamb = -40C to +85C or Philips parts when Tamb = -40C to +125C, see DC Electrical Characteristics table on previous page. 8. The operating supply current is measured with all output pins disconnected; XTAL1 driven with tr = tf = 10ns; VIL = VSS + 0.5V; VIH = VCC - 0.5V; XTAL2 not connected; EA = RST = Port 0 = VCC. 9. The idle mode supply current is measured with all output pins disconnected; XTAL1 driven with tr = tf = 10ns; VIL = VSS + 0.5V; VIH = VCC - 0.5V; XTAL2 not connected; EA = Port 0 = VCC; RST = VSS. 10. The power-down current is measured with all output pins disconnected, XTAL2 not connected, EA = Port 0 = VCC; RST = VSS. 11. Under steady state (non-transient) conditions, IOL must be externally limited as follows: 15mA Maximum IOL per port pin: 26mA Maximum IOL per 8-bit port: 67mA Maximum IOL total for all outputs: If IOL exceeds the test condition, VOL may exceed the related specification. Pins are not guaranteed to sink current greater than the listed test conditions. 12. Pin capacitance for the ceramic DIP package is 15pF maximum.
1996 Aug 16
11
Philips Semiconductors
Product specification
CMOS single-chip 8-bit microcontrollers
80C31/80C51/87C51
DC ELECTRICAL CHARACTERISTICS FOR PHILIPS NORTH AMERICA DEVICES (SC80C31 AND SC80C51)
Tamb = 0C to +70C or -40C to +85C, VCC = 5V 10%; VSS = 0V SYMBOL VIL VIH VIH1 VOL VOL1 VOH VOH1 IIL ITL ILI ICC Input low voltage Input high voltage (ports 0, 1, 2, 3, EA) Input high voltage, XTAL1, RST Output low voltage, ports 1, 2, 38 Output low voltage, port 0, ALE, PSEN8, 7 Output high voltage, ports 1, 2, 3 3 Output high voltage (port 0 in external bus mode), ALE9, PSEN3 Logical 0 input current, ports 1, 2, 3 Logical 1-to-0 transition current, ports 1, 2, 36 Input leakage current, port 0 Power supply current (see Figure 8): Active mode @ 16MHz5 Idle mode @ 16MHz5 Power-down mode Internal reset pull-down resistor Pin capacitance10 (except EA) VCC = 4.5V IOL = 1.6mA2 VCC = 4.5V IOL = 3.2mA2 VCC = 4.5V IOH = -30A VCC = 4.5V IOH = -3.2mA VIN = 0.4V VIN = 2.0V See note 4 0.45 < VIN < VCC - 0.3 See note 5 Tamb = 0 to +70C Tamb = -40 to +85C 40 11.5 1.3 3 32 5 50 75 225 15 VCC - 0.7 VCC - 0.7 -1 -50 -650 10 PARAMETER TEST CONDITIONS 4.5V < VCC < 5.5V LIMITS MIN -0.5 0.2VCC+0.9 0.7VCC TYP1 UNIT MAX 0.2VCC-0.1 VCC+0.5 VCC+0.5 0.4 0.4 V V V V V V V A A A A A A A k pF
RRST CIO
NOTES: 1. Typical ratings are not guaranteed. The values listed are at room temperature, 5V. 2. Capacitive loading on ports 0 and 2 may cause spurious noise to be superimposed on the VOLs of ALE and ports 1 and 3. The noise is due to external bus capacitance discharging into the port 0 and port 2 pins when these pins make 1-to-0 transitions during bus operations. In the worst cases (capacitive loading > 100pF), the noise pulse on the ALE pin may exceed 0.8V. In such cases, it may be desirable to qualify ALE with a Schmitt Trigger, or use an address latch with a Schmitt Trigger STROBE input. IOL can exceed these conditions provided that no single output sinks more than 5mA and no more than two outputs exceed the test conditions. 3. Capacitive loading on ports 0 and 2 may cause the VOH on ALE and PSEN to momentarily fall below the (VCC-0.7) specification when the address bits are stabilizing. 4. Pins of ports 1, 2 and 3 source a transition current when they are being externally driven from 1 to 0. The transition current reaches its maximum value when VIN is approximately 2V. 5. See Figures 9 through 12 for ICC test conditions. Active Mode: ICC = 1.5 x FREQ + 8.0; Idle Mode: ICC = 0.14 x FREQ +2.31; See Figure 8. 6. This value applies to Tamb = 0C to +70C. For Tamb = -40C to +85C, ITL = -750A. 7. Load capacitance for port 0, ALE, and PSEN = 100pF, load capacitance for all other outputs = 80pF. 8. Under steady state (non-transient) conditions, IOL must be externally limited as follows: 15mA (*NOTE: This is 85C specification.) Maximum IOL per port pin: Maximum IOL per 8-bit port: 26mA 71mA Maximum total IOL for all outputs: If IOL exceeds the test condition, VOL may exceed the related specification. Pins are not guaranteed to sink current greater than the listed test conditions. 9. ALE is tested to VOH1, except when ALE is off then VOH is the voltage specification. 10. Pin capacitance is characterized but not tested. Pin capacitance is less than 25pF. Pin capacitance of ceramic package is less than 15pF (except EA it is 25pF).
1996 Aug 16
12
Philips Semiconductors
Product specification
CMOS single-chip 8-bit microcontrollers
80C31/80C51/87C51
Tamb = 0C to +70C or -40C to +85C, VCC = 5V 10%, VSS = 0V (SC87C51 12, 16 and 24MHz versions); For SC87C51 (33MHz only) Tamb = = 0C to +70C, VCC = 5V 5%
AC ELECTRICAL CHARACTERISTICS FOR SC87C51 12-33MHz PHILIPS NORTH AMERICA DEVICES
VARIABLE CLOCK3 SYMBOL 1/tCLCL FIGURE Oscillator frequency: SC87C51 PARAMETER Speed Versions C G P Y MIN 3.5 3.5 3.5 3.5 2tCLCL-40 tCLCL-13 tCLCL-20 4tCLCL-65 tCLCL-13 3tCLCL-20 3tCLCL-45 0 tCLCL-10 5tCLCL-55 10 MAX 12 16 24 33 UNIT MHz MHz MHz MHz ns ns ns ns ns ns ns ns ns ns ns
tLHLL tAVLL tLLAX tLLIV tLLPL tPLPH tPLIV tPXIX tPXIZ tAVIV tPLAZ Data Memory tRLRH tWLWH tRLDV tRHDX tRHDZ tLLDV tAVDV tLLWL tAVWL tQVWX tWHQX tRLAZ tWHLH External Clock tCHCX tCLCX tCLCH tCHCL
1 1 1 1 1 1 1 1 1 1 1
ALE pulse width Address valid to ALE low Address hold after ALE low ALE low to valid instruction in ALE low to PSEN low PSEN pulse width PSEN low to valid instruction in Input instruction hold after PSEN Input instruction float after PSEN Address to valid instruction in PSEN low to address float
2, 3 2, 3 2, 3 2, 3 2, 3 2, 3 2, 3 2, 3 2, 3 2, 3 2, 3 2, 3 2, 3
RD pulse width WR pulse width RD low to valid data in Data hold after RD Data float after RD ALE low to valid data in Address to valid data in ALE low to RD or WR low Address valid to WR low or RD low Data valid to WR transition Data hold after WR RD low to address float RD or WR high to ALE high
6tCLCL-100 6tCLCL-100 5tCLCL-90 0 2tCLCL-28 8tCLCL-150 9tCLCL-165 3tCLCL-50 4tCLCL-75 tCLCL-20 tCLCL-20 0 tCLCL-20 tCLCL+25 3tCLCL+50
ns ns ns ns ns ns ns ns ns ns ns ns ns
5 5 5 5
High time Low time Rise time Fall time
12 12 20 20
ns ns ns ns
NOTES: 1. Parameters are valid over operating temperature range unless otherwise specified. 2. Load capacitance for port 0, ALE, and PSEN = 100pF, load capacitance for all other outputs = 80pF. 3. For all Philips North America speed versions only. 4. Interfacing the 87C51 to devices with float times up to 50ns is permitted. This limited bus contention will not cause damage to port 0 drivers.
1996 Aug 16
13
Philips Semiconductors
Product specification
CMOS single-chip 8-bit microcontrollers
80C31/80C51/87C51
AC ELECTRICAL CHARACTERISTICS FOR PHILIPS DEVICES
Tamb = 0C to +70C, VCC = 5V 20%, VSS = 0V (PCB80C31/51, PCF80C31/51)1, 2, 4, 5 VARIABLE CLOCK3 SYMBOL 1/tCLCL FIGURE PARAMETER Oscillator frequency: Speed Versions PCB8031/51 -2 PCA/PCB/PCF80C31/51 -3 PCB/PCF80C31/51 -4 PCB/FB80C31/51 -5 1 1 1 1 1 1 1 1 1 1 1 ALE pulse width Address valid to ALE low Address hold after ALE low ALE low to valid instruction in ALE low to PSEN low PSEN pulse width PSEN low to valid instruction in Input instruction hold after PSEN Input instruction float after PSEN Address to valid instruction in PSEN low to address float 0 tCLCL-25 5tCLCL-80 10 tCLCL-25 3tCLCL-45 3tCLCL-60 MIN 0.5 1.2 1.2 1.2 2tCLCL-40 tCLCL-25 tCLCL-25 4tCLCL-65 MAX 12 16 24 33 UNIT MHz MHz MHz MHz ns ns ns ns ns ns ns ns ns ns ns
tLHLL tAVLL tLLAX tLLIV tLLPL tPLPH tPLIV tPXIX tPXIZ tAVIV tPLAZ Data Memory tRLRH tWLWH tRLDV tRHDX tRHDZ tLLDV tAVDV tLLWL tAVWL tQVWX tWHQX tRLAZ tWHLH External Clock tCHCX tCLCX tCLCH tCHCL
2, 3 2, 3 2, 3 2, 3 2, 3 2, 3 2, 3 2, 3 2, 3 2, 3 2, 3 2, 3 2, 3
RD pulse width WR pulse width RD low to valid data in Data hold after RD Data float after RD ALE low to valid data in Address to valid data in ALE low to RD or WR low Address valid to WR low or RD low Data valid to WR transition Data hold after WR RD low to address float RD or WR high to ALE high
6tCLCL-100 6tCLCL-100 5tCLCL-90 0 2tCLCL-28 8tCLCL-150 9tCLCL-165 3tCLCL-50 4tCLCL-75 tCLCL-30 tCLCL-25 0 tCLCL-25 tCLCL+25 3tCLCL+50
ns ns ns ns ns ns ns ns ns ns ns ns ns
5 5 5 5
High time Low time Rise time Fall time
15 15 20 20
ns ns ns ns
NOTES: 1. Parameters are valid over operating temperature range unless otherwise specified. 2. Load capacitance for port 0, ALE, and PSEN = 100pF, load capacitance for all other outputs = 80pF. 3. For all Philips speed versions only. 4. Interfacing the 80C31/51 to devices with float times up to 30ns is permitted. This limited bus contention will not cause damage to port 0 drivers. 5. VCC = 5V 10% for 33MHz.
1996 Aug 16
14
Philips Semiconductors
Product specification
CMOS single-chip 8-bit microcontrollers
80C31/80C51/87C51
AC ELECTRICAL CHARACTERISTICS FOR PHILIPS NORTH AMERICA DEVICES (SC80C31 AND SC80C51)
Tamb = 0C to +70C or -40C to +85C, VCC = 5V 10%, VSS = 0V1, 2, 3 SYMBOL 1/tCLCL tLHLL tAVLL tLLAX tLLIV tLLPL tPLPH tPLIV tPXIX tPXIZ tAVIV tPLAZ Data Memory tRLRH tWLWH tRLDV tRHDX tRHDZ tLLDV tAVDV tLLWL tAVWL tQVWX tWHQX tQVWH tRLAZ tWHLH External Clock tCHCX tCLCX tCLCH tCHCL Shift Register tXLXL tQVXH tXHQX tXHDX 4 4 4 4 Serial port clock cycle time Output data setup to clock rising edge Output data hold after clock rising edge Input data hold after clock rising edge 750 492 8 0 12tCLCL 10tCLCL-133 2tCLCL-117 0 ns ns ns ns 5 5 5 5 High time Low time Rise time Fall time 20 20 20 20 20 20 tCLCL-tCLCX tCLCL-tCHCX 20 20 ns ns ns ns 2, 3 2, 3 2, 3 2, 3 2, 3 2, 3 2, 3 2, 3 2, 3 2, 3 2, 3 3 2, 3 2, 3 RD pulse width WR pulse width RD low to valid data in Data hold after RD Data float after RD ALE low to valid data in Address to valid data in ALE low to RD or WR low Address valid to WR low or RD low Data valid to WR transition Data hold after WR Data valid to WR high RD low to address float RD or WR high to ALE high 23 137 122 13 13 287 0 103 tCLCL-40 0 65 350 397 239 3tCLCL-50 4tCLCL-130 tCLCL-50 tCLCL-50 7tCLCL-150 0 tCLCL+40 275 275 147 0 2tCLCL-60 8tCLCL-150 9tCLCL-165 3tCLCL+50 6tCLCL-100 6tCLCL-100 5tCLCL-165 ns ns ns ns ns ns ns ns ns ns ns ns ns ns FIGURE 1 1 1 1 1 1 1 1 1 1 1 1 PARAMETER Oscillator frequency Speed versions : C, G ALE pulse width Address valid to ALE low Address hold after ALE low ALE low to valid instruction in ALE low to PSEN low PSEN pulse width PSEN low to valid instruction in4 0 37 207 10 32 142 82 0 tCLCL-25 5tCLCL-105 10 85 22 32 150 tCLCL-30 3tCLCL-45 3tCLCL-105 16MHz CLOCK MIN MAX VARIABLE CLOCK MIN 3.5 2tCLCL-40 tCLCL-40 tCLCL-30 4tCLCL-100 MAX 16 UNIT MHz ns ns ns ns ns ns ns ns ns ns ns
Input instruction hold after PSEN Input instruction float after PSEN Address to valid instruction in4 PSEN low to address float
tXHDV 4 Clock rising edge to input data valid 492 10tCLCL-133 ns NOTES: 1. Parameters are valid over operating temperature range unless otherwise specified. 2. Load capacitance for port 0, ALE, and PSEN = 100pF, load capacitance for all other outputs = 80pF. 3. Interfacing the 80C31/51 to devices with float times up to 45ns is permitted. This limited bus contention will not cause damage to Port 0 drivers. 4. See application note AN457 for external memory interfacing.
1996 Aug 16
15
Philips Semiconductors
Product specification
CMOS single-chip 8-bit microcontrollers
80C31/80C51/87C51
AC ELECTRICAL CHARACTERISTICS FOR PHILIPS NORTH AMERICA DEVICES (SC80C31 AND SC80C51)
Tamb = 0C to +70C or -40C to +85C, VCC = 5V 10%, VSS = 0V1, 2, 3 SYMBOL 1/tCLCL FIGURE 1 PARAMETER Oscillator frequency Speed versions : P (24MHz) : Y (33MHz) ALE pulse width Address valid to ALE low Address hold after ALE low ALE low to valid instruction in ALE low to PSEN low PSEN pulse width PSEN low to valid instruction in Input instruction hold after PSEN Input instruction float after PSEN Address to valid instruction in PSEN low to address float RD pulse width WR pulse width RD low to valid data in Data hold after RD Data float after RD ALE low to valid data in Address to valid data in ALE low to RD or WR low Address valid to WR low or RD low Data valid to WR transition Data hold after WR Data valid to WR high RD low to address float RD or WR high to ALE high High time Low time Rise time Fall time Serial port clock cycle time Output data setup to clock rising edge Output data hold after clock rising edge Input data hold after clock rising edge 505 283 3 0 17 17 17 5 5 12tCLCL 10tCLCL-133 2tCLCL-80 0 0 75 92 12 17 162 0 67 tCLCL-25 17 17 0 55 183 210 175 3tCLCL-50 4tCLCL-75 tCLCL-30 tCLCL-25 7tCLCL-130 0 tCLCL+25 tCLCL-tCLCX tCLCL-tCHCX 5 5 360 167 5 150 150 118 0 2tCLCL-28 8tCLCL-150 9tCLCL-165 3tCLCL+50 40 45 0 5 80 0 55 0 17 128 10 6tCLCL-100 6tCLCL-100 5tCLCL-90 0 32 90 105 140 17 80 65 0 tCLCL-25 5tCLCL-80 10 82 82 60 24MHz CLOCK MIN 3.5 43 17 17 102 tCLCL-25 3tCLCL-45 3tCLCL-60 0 5 70 10 MAX 24 3.5 2tCLCL-40 tCLCL-25 tCLCL-25 4tCLCL-65 5 45 30 55 21 5 33 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns VARIABLE CLOCK4 MIN 3.5 MAX 33 MHz 33MHz CLOCK MIN MAX UNIT
tLHLL tAVLL tLLAX tLLIV tLLPL tPLPH tPLIV tPXIX tPXIZ tAVIV tPLAZ Data Memory tRLRH tWLWH tRLDV tRHDX tRHDZ tLLDV tAVDV tLLWL tAVWL tQVWX tWHQX tQVWH tRLAZ tWHLH tCHCX tCLCX tCLCH tCHCL Shift Register tXLXL tQVXH tXHQX tXHDX
1 1 1 1 1 1 1 1 1 1 1 2, 3 2, 3 2, 3 2, 3 2, 3 2, 3 2, 3 2, 3 2, 3 2, 3 2, 3 3 2, 3 2, 3 5 5 5 5 4 4 4 4
External Clock
tXHDV 4 Clock rising edge to input data valid 283 10tCLCL-133 167 ns NOTES: 1. Parameters are valid over operating temperature range unless otherwise specified. 2. Load capacitance for port 0, ALE, and PSEN = 100pF, load capacitance for all other outputs = 80pF. 3. Interfacing the SC80C31/51 to devices with float times up to 45ns is permitted. This limited bus contention will not cause damage to Port 0 drivers. 4. Variable clock is specified for oscillator frequencies greater than 16MHz to 33MHz. For frequencies equal or less than 16MHz, see 16MHz "AC Electrial Characteristics", page 15. 1996 Aug 16 16
Philips Semiconductors
Product specification
CMOS single-chip 8-bit microcontrollers
80C31/80C51/87C51
EXPLANATION OF THE AC SYMBOLS
Each timing symbol has five characters. The first character is always `t' (= time). The other characters, depending on their positions, indicate the name of a signal or the logical status of that signal. The designations are: A - Address C - Clock D - Input data H - Logic level high I - Instruction (program memory contents) L - Logic level low, or ALE P - PSEN Q - Output data R - RD signal t - Time V - Valid W - WR signal X - No longer a valid logic level Z - Float Examples: tAVLL = Time for address valid to ALE low. tLLPL= Time for ALE low to PSEN low.
tLHLL
ALE
tAVLL
tLLPL
PSEN
tPLPH tLLIV tPLIV tPLAZ tPXIX
INSTR IN
tLLAX
tPXIZ
PORT 0
A0-A7
A0-A7
tAVIV
PORT 2 A0-A15 A8-A15
SU00006
Figure 1. External Program Memory Read Cycle
ALE
tWHLH
PSEN
tLLDV tLLWL
RD
tRLRH
tAVLL
PORT 0
tLLAX tRLAZ
A0-A7 FROM RI OR DPL
tRLDV tRHDX
DATA IN
tRHDZ
A0-A7 FROM PCL
INSTR IN
tAVWL tAVDV
PORT 2 P2.0-P2.7 OR A8-A15 FROM DPH A0-A15 FROM PCH
SU00007
Figure 2. External Data Memory Read Cycle
1996 Aug 16
17
Philips Semiconductors
Product specification
CMOS single-chip 8-bit microcontrollers
80C31/80C51/87C51
ALE
tWHLH
PSEN
tLLWL
WR
tWLWH
tAVLL
PORT 0
tLLAX
tQVWX
tWHQX
A0-A7 FROM RI OR DPL
DATA OUT
A0-A7 FROM PCL
INSTR IN
tAVWL
PORT 2 P2.0-P2.7 OR A8-A15 FROM DPH A0-A15 FROM PCH
SU00008
Figure 3. External Data Memory Write Cycle
INSTRUCTION ALE
0
1
2
3
4
5
6
7
8
tXLXL
CLOCK
tQVXH
OUTPUT DATA 0 WRITE TO SBUF
tXHQX
1 2 3 4 5 6 7
tXHDV
INPUT DATA VALID CLEAR RI VALID
tXHDX
SET TI VALID VALID VALID VALID VALID VALID
SET RI
SU00027
Figure 4. Shift Register Mode Timing
VCC-0.5 0.45V
0.7VCC 0.2VCC-0.1
tCHCL
tCLCX tCLCL
tCHCX tCLCH
SU00009
Figure 5. External Clock Drive
1996 Aug 16
18
Philips Semiconductors
Product specification
CMOS single-chip 8-bit microcontrollers
80C31/80C51/87C51
VCC-0.5
0.2VCC+0.9 0.2VCC-0.1
0.45V
NOTE: AC inputs during testing are driven at VCC -0.5 for a logic `1' and 0.45V for a logic `0'. Timing measurements are made at VIH min for a logic `1' and VIL max for a logic `0'.
SU00010
Figure 6. AC Testing Input/Output
VLOAD+0.1V VLOAD VLOAD-0.1V
TIMING REFERENCE POINTS
VOH-0.1V VOL+0.1V
NOTE: For timing purposes, a port is no longer floating when a 100mV change from load voltage occurs, and begins to float when a 100mV change from the loaded VOH/VOL level occurs. IOH/IOL 20mA.
SU00011
Figure 7. Float Waveform
MAX ACTIVE MODE (ICCMAX = 1.43 freq + 1.9) 45
40
35
30
TYP ACTIVE MODE 25
ICC mA
20
15
10 MAX IDLE MODE 5 TYP IDLE MODE
4MHz
8MHz
12MHz
16MHz
20MHz
24MHz
30MHz
33MHz
FREQ AT XTAL1
SU00012
Figure 8. ICC vs. FREQ Valid only within frequency specifications of the device under test
1996 Aug 16
19
Philips Semiconductors
Product specification
CMOS single-chip 8-bit microcontrollers
80C31/80C51/87C51
VCC ICC VCC VCC P0 EA (NC) CLOCK SIGNAL XTAL2 XTAL1 VSS (NC) CLOCK SIGNAL XTAL2 XTAL1 VSS VCC RST P0 EA VCC
VCC ICC
VCC
RST
SU00719
SU00720
Figure 9. ICC Test Condition, Active Mode All other pins are disconnected
Figure 10. ICC Test Condition, Idle Mode All other pins are disconnected
VCC-0.5 0.45V
0.7VCC 0.2VCC-0.1
tCHCL
tCLCX tCLCL
tCHCX tCLCH
SU00015
Figure 11. Clock Signal Waveform for ICC Tests in Active and Idle Modes tCLCH = tCHCL = 5ns
VCC ICC VCC RST P0 EA (NC) XTAL2 XTAL1 VSS VCC
SU00016
Figure 12. ICC Test Condition, Power Down Mode All other pins are disconnected. VCC = 2V to 5.5V
1996 Aug 16
20
Philips Semiconductors
Product specification
CMOS single-chip 8-bit microcontrollers
80C31/80C51/87C51
EPROM CHARACTERISTICS
The 87C51 is programmed by using a modified Quick-Pulse ProgrammingTM algorithm. It differs from older methods in the value used for VPP (programming supply voltage) and in the width and number of the ALE/PROG pulses. The 87C51 contains two signature bytes that can be read and used by an EPROM programming system to identify the device. The signature bytes identify the device as an 87C51 manufactured by Philips Corporation. Table 3 shows the logic levels for reading the signature bytes, and for programming the program memory, the encryption table, and the security bits. The circuit configuration and waveforms for quick-pulse programming are shown in Figures 13 and 14. Figure 15 shows the circuit configuration for normal program memory verification.
Program Verification
If security bit 2 has not been programmed, the on-chip program memory can be read out for program verification. The address of the program memory locations to be read is applied to ports 1 and 2 as shown in Figure 15. The other pins are held at the `Verify Code Data' levels indicated in Table 3. The contents of the address location will be emitted on port 0. External pull-ups are required on port 0 for this operation. If the encryption table has been programmed, the data presented at port 0 will be the exclusive NOR of the program byte with one of the encryption bytes. The user will have to know the encryption table contents in order to correctly decode the verification data. The encryption table itself cannot be read out. Reading the Signature Bytes The signature bytes are read by the same procedure as a normal verification of locations 030H and 031H, except that P3.6 and P3.7 need to be pulled to a logic low. The values are: (030H) = 15H indicates manufactured by Philips (031H) = 92H indicates 87C51
Quick-Pulse Programming
The setup for microcontroller quick-pulse programming is shown in Figure 13. Note that the 87C51 is running with a 4 to 6MHz oscillator. The reason the oscillator needs to be running is that the device is executing internal address and program data transfers. The address of the EPROM location to be programmed is applied to ports 1 and 2, as shown in Figure 13. The code byte to be programmed into that location is applied to port 0. RST, PSEN and pins of ports 2 and 3 specified in Table 3 are held at the `Program Code Data' levels indicated in Table 3. The ALE/PROG is pulsed low 25 times as shown in Figure 14. To program the encryption table, repeat the 25 pulse programming sequence for addresses 0 through 1FH, using the `Pgm Encryption Table' levels. Do not forget that after the encryption table is programmed, verification cycles will produce only encrypted data. To program the security bits, repeat the 25 pulse programming sequence using the `Pgm Security Bit' levels. After one security bit is programmed, further programming of the code memory and encryption table is disabled. However, the other security bit can still be programmed. Note that the EA/VPP pin must not be allowed to go above the maximum specified VPP level for any amount of time. Even a narrow glitch above that voltage can cause permanent damage to the device. The VPP source should be well regulated and free of glitches and overshoot.
Program/Verify Algorithms
Any algorithm in agreement with the conditions listed in Table 3, and which satisfies the timing specifications, is suitable.
Erasure Characteristics
Erasure of the EPROM begins to occur when the chip is exposed to light with wavelengths shorter than approximately 4,000 angstroms. Since sunlight and fluorescent lighting have wavelengths in this range, exposure to these light sources over an extended time (about 1 week in sunlight, or 3 years in room level fluorescent lighting) could cause inadvertent erasure. For this and secondary effects, it is recommended that an opaque label be placed over the window. For elevated temperature or environments where solvents are being used, apply Kapton tape Fluorglas part number 2345-5, or equivalent. The recommended erasure procedure is exposure to ultraviolet light (at 2537 angstroms) to an integrated dose of at least 15W-sec/cm2. Exposing the EPROM to an ultraviolet lamp of 12,000W/cm2 rating for 20 to 39 minutes, at a distance of about 1 inch, should be sufficient. Erasure leaves the array in an all 1s state.
Table 3. EPROM Programming Modes
MODE Read signature Program code data Verify code data Pgm encryption table Pgm security bit 1 RST 1 1 1 1 1 PSEN 0 0 0 0 0 ALE/PROG 1 0* 1 0* 0* EA/VPP 1 VPP 1 VPP VPP P2.7 0 1 0 1 1 P2.6 0 0 0 0 1 P3.7 0 1 1 1 1 P3.6 0 1 1 0 1
Pgm security bit 2 1 0 0* VPP 1 1 0 0 NOTES: 1. `0' = Valid low for that pin, `1' = valid high for that pin. 2. VPP = 12.75V +0.25V. 3. VCC = 5V10% during programming and verification. 4. *ALE/PROG receives 25 programming pulses while VPP is held at 12.75V. Each programming pulse is low for 100s (10s) and high for a minimum of 10s.
TMTrademark phrase of Intel Corporation. 1996 Aug 16 21
Philips Semiconductors
Product specification
CMOS single-chip 8-bit microcontrollers
80C31/80C51/87C51
+5V
VCC A0-A7 1 1 1 P1 RST P3.6 P3.7 XTAL2 4-6MHz XTAL1 VSS 87C51 P0 PGM DATA +12.75V 25 100s PULSES TO GROUND 0 1 0 A8-A11
EA/VPP ALE/PROG PSEN P2.7 P2.6 P2.0-P2.3
SU00017
Figure 13. Programming Configuration
1 ALE/PROG: 0
25 PULSES
1 ALE/PROG: 0
10s MIN
100s+10
SU00018
Figure 14. PROG Waveform
+5V
VCC A0-A7 1 1 1 P1 RST P3.6 P3.7 XTAL2 4-6MHz XTAL1 VSS 87C51 P0 PGM DATA 1 1 0 0 ENABLE 0 A8-A11
EA/VPP ALE/PROG PSEN P2.7 P2.6 P2.0-P2.3
SU00019
Figure 15. Program Verification
1996 Aug 16
22
Philips Semiconductors
Product specification
CMOS single-chip 8-bit microcontrollers
80C31/80C51/87C51
EPROM PROGRAMMING AND VERIFICATION CHARACTERISTICS
Tamb = 21C to +27C, VCC = 5V10%, VSS = 0V (See Figure 16) SYMBOL VPP IPP 1/tCLCL tAVGL tGHAX tDVGL tGHDX tEHSH tSHGL tGHSL tGLGH tAVQV tELQZ tEHQZ tGHGL PARAMETER Programming supply voltage Programming supply current Oscillator frequency Address setup to PROG low Address hold after PROG Data setup to PROG low Data hold after PROG P2.7 (ENABLE) high to VPP VPP setup to PROG low VPP hold after PROG PROG width Address to data valid ENABLE low to data valid Data float after ENABLE PROG high to PROG low 0 10 4 48tCLCL 48tCLCL 48tCLCL 48tCLCL 48tCLCL 10 10 90 110 48tCLCL 48tCLCL 48tCLCL s s s s MIN 12.5 MAX 13.0 50 6 UNIT V mA MHz
PROGRAMMING* P1.0-P1.7 P2.0-P2.4 ADDRESS
VERIFICATION* ADDRESS
tAVQV
PORT 0 DATA IN DATA OUT
tDVGL tAVGL
ALE/PROG
tGHDX tGHAX
tGLGH tSHGL
tGHGL tGHSL
LOGIC 1 EA/VPP LOGIC 0
LOGIC 1
tEHSH
P2.7 ENABLE
tELQV
tEHQZ
SU00020
NOTE:
* FOR PROGRAMMING VERIFICATION SEE FIGURE 13. FOR VERIFICATION CONDITIONS SEE FIGURE 15.
Figure 16. EPROM Programming and Verification
1996 Aug 16
23
0590B
1996 Aug 16
SEE NOTE 6 0.098 (2.49) 0.040 (1.02)
Philips Semiconductors
CMOS single-chip 8-bit microcontrollers
853-0590B 06688
0.098 (2.49) 0.040 (1.02)
NOTES: 1. Controlling dimension: Inches. Millimeters are shown in parentheses. 2. Dimension and tolerancing per ANSI Y14. 5M-1982. 3. "T", "D", and "E" are reference datums on the body and include allowance for glass overrun and meniscus on the seal line, and lid to base mismatch. 4. These dimensions measured with the leads constrained to be perpendicular to plane T. 5. Pin numbers start with Pin #1 and continue counterclockwise to Pin #40 when viewed from the top. 6. Denotes window location for EPROM products.
-E-
0.598 (15.19) 0.571 (14.50)
PIN # 1 2.087 (53.01) 2.038 (51.77)
0.100 (2.54) BSC
-D-
40-PIN (600 mils wide) CERAMIC DUAL IN-LINE (F) PACKAGE (WITH WINDOW (FA) PACKAGE)
24
0.225 (5.72) MAX. 0.175 (4.45) 0.145 (3.68) 0.165 (4.19) 0.125 (3.18) 0.055 (1.40) 0.020 (0.51) ED 0.010 (0.254) 0.015 (0.38) 0.010 (0.25)
0.070 (1.78) 0.050 (1.27)
0.620 (15.75) 0.590 (14.99) (NOTE 4)
-T-
SEATING PLANE
BSC 0.600 (15.24) (NOTE 4) 0.695 (17.65) 0.600 (15.24)
0.023 (0.58) 0.015 (0.38)
T
80C31/80C51/87C51
Product specification
1472A
1996 Aug 16
3.05 (0.120) 2.29 (0.090) 0.38 (0.015) 6
Philips Semiconductors
CMOS single-chip 8-bit microcontrollers
853-1472A 05854
1.02 (0.040) X 45 CHAMFER 45
17.65 (0.695) 17.40 (0.685) 16.89 (0.665) 16.00 (0.630) 3
NOTES: 1. All dimensions and tolerances to conform to ANSI Y14.5-1982. 2. UV window is optional. 3. Dimensions do not include glass protrusion. Glass protrusion to be 0.005 inches maximum on each side. 4. Controlling dimension millimeters. 5. All dimensions and tolerances include lead trim offset and lead plating finish. 6. Backside solder relief is optional and dimensions are for reference only.
0.51 (0.02) X 45 17.65 (0.695) 17.40 (0.685) 16.89 (0.665) 16.00 (0.630) 3 6
2
44-PIN CERQUAD J-BEND (K) PACKAGE
3 X 0.63 (0.025) R MIN.
4.83 (0.190) 3.94 (0.155)
SEATING PLANE
0.73 + 0.08 (0.029 + 0.003) 1.27 (0.050) TYP. 0.25 (0.010) R MIN. 1.52 (0.060) REF. 45 TYP. 4 PLACES 0.15 (0.006) MIN.
90
25
1.02 + 0.25 (0.040 + 0.010) SEE DETAIL A 0.482 (0.019 + 0.002) SEATING PLANE BASE PLANE
+ 5 -10
17.65 (0.656) 17.40 (0.685)
1.27 (0.050)
40X
0.076 (0.003) MIN.
4.83 (0.190) 3.94 (0.155)
SEATING PLANE
SEE DETAIL B
12.7 (0.500) NOMINAL
0.25 (0.010) 0.15 (0.006)
0.508 (0.020) R MIN.
80C31/80C51/87C51
8.13 (0.320) 7.37 (0.290)
8.13 (0.320) 7.37 (0.290)
DETAIL A TYP. ALL SIDES mm/(inch)
DETAIL B mm/(inch)
Product specification
Philips Semiconductors
Product specification
CMOS single-chip 8-bit microcontrollers
80C31/80C51/87C51
DIP40: plastic dual in-line package; 40 leads (600 mil)
SOT129-1
1996 Aug 16
26
Philips Semiconductors
Product specification
CMOS single-chip 8-bit microcontrollers
80C31/80C51/87C51
PLCC44: plastic leaded chip carrier; 44 leads
SOT187-2
1996 Aug 16
27
Philips Semiconductors
Product specification
CMOS single-chip 8-bit microcontrollers
80C31/80C51/87C51
QFP44: plastic quad flat package; 44 leads (lead length 1.3 mm); body 10 x 10 x 1.75 mm
SOT307-2
1996 Aug 16
28
Philips Semiconductors
Product specification
CMOS single-chip 8-bit microcontrollers
80C31/80C51/87C51
NOTES
1996 Aug 16
29
Philips Semiconductors
Product specification
CMOS single-chip 8-bit microcontrollers
80C31/80C51/87C51
DEFINITIONS
Data Sheet Identification
Objective Specification
Product Status
Formative or in Design
Definition
This data sheet contains the design target or goal specifications for product development. Specifications may change in any manner without notice. This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. This data sheet contains Final Specifications. Philips Semiconductors reserves the right to make changes at any time without notice, in order to improve design and supply the best possible product.
Preliminary Specification
Preproduction Product
Product Specification
Full Production
Philips Semiconductors and Philips Electronics North America Corporation reserve the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. LIFE SUPPORT APPLICATIONS Philips Semiconductors and Philips Electronics North America Corporation Products are not designed for use in life support appliances, devices, or systems where malfunction of a Philips Semiconductors and Philips Electronics North America Corporation Product can reasonably be expected to result in a personal injury. Philips Semiconductors and Philips Electronics North America Corporation customers using or selling Philips Semiconductors and Philips Electronics North America Corporation Products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors and Philips Electronics North America Corporation for any damages resulting from such improper use or sale. Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California 94088-3409 Telephone 800-234-7381 Philips Semiconductors and Philips Electronics North America Corporation register eligible circuits under the Semiconductor Chip Protection Act. (c) Copyright Philips Electronics North America Corporation 1996 All rights reserved. Printed in U.S.A.

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